D-TA Elert Header
Technical Seminar: 10 Gigabit Sensor Processing Simplifies ISR System Development

bulletMay 15, 2014

bullet10 am to 12 noon.......... Click here to register

bulletHyatt Fairfax at Fair Lakes
bullet12777 Fair Lakes Cir
bulletFairfax, VA, 22033

bulletDoD budget pressures and time-to-deployment pressures are seriously challenging
bulletthe current paradigm of bus-board based approach for sensor equipment development.
bulletThe prime contractors are finding that to assemble, integrate, develop and test bus-boards
bulletbased design for complex sensor systems are becoming cost & time prohibitive.

bulletThis webinar will discuss a new paradigm based on System-Level Sensor Interface COTS
bullet& 10 Gigabit data backbone the connects seamlessly to multi-core servers for real-time
bulletapplication development. In addition to drastic savings in cost and deployment time,
bulletthe approach leads to scalable and future-proof architectures.

bulletCome & see live demonstrations of:
bullet1. World’s most advanced open-architecture EW solution; and,
bullet2. Real-Time acquisition, recording & processing of Ultra-Wideband
bulletbulletRF signals

board images
www.d-ta.com 1-877-382-3222
D-TA Elert Footer